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FEATURES
n n n n n n n n n n
LTC2655 Quad I2C 16-/12-Bit Rail-to-Rail DACs with 10ppm/C Max Reference DESCRIPTION
The LTC(R)2655 is a family of Quad I2C 16-/12-Bit Rail-toRail DACs with integrated 10ppm/C max reference. The DACs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. The LTC2655-L has a full-scale output of 2.5V with the integrated reference and operates from a single 2.7V to 5.5V supply. The LTC2655-H has a full-scale output of 4.096V with the integrated reference and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. The parts use the 2-wire I2C compatible serial interface. The LTC2655 operates in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum clock rate of 400kHz). The LTC2655 incorporates a power-on reset circuit that is controlled by the PORSEL pin. If PORSEL is tied to GND the DACs power-on reset to zero-scale. If PORSEL is tied to VCC, the DACs power-on reset to mid-scale.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 6891433 and 7671770.
Integrated Reference 10ppm/C Max Maximum INL Error: 4LSB at 16 Bits Guaranteed Monotonic Over Temperature Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2655-L) Integrated Reference Buffers Ultralow Crosstalk Between DACs (<1nV*s) Power-On-Reset to Zero-Scale/Mid-Scale Asynchronous DAC Update Pin Tiny 20-Lead 4mm x 4mm QFN and 16-Lead Narrow SSOP packages
APPLICATIONS
n n n n n
Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment Automotive
BLOCK DIAGRAM
REFCOMP GND REFLO REGISTER REGISTER REGISTER REGISTER VOUTA DAC A DAC D VOUTD INL (LSB) INTERNAL REFERENCE REFIN/OUT
INL Curve
VCC 4 3 2 1 0 -1 DAC C VOUTC -2 -3 POWER-ON RESET PORSEL -4 128 16384 32768 CODE 49152 65535
2655 TA01b
VCC = 5V
REGISTER
REGISTER
REGISTER
VOUTB CA0 CA1
DAC B
32-BIT SHIFT REGISTER CA2 SCL LDAC 2-WIRE INTERFACE
REGISTER
SDA
2655 BD
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LTC2655 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... -0.3V to 6V SCL, SDA, LDAC, REFLO .............................. -0.3V to 6V VOUTA to VOUTD ................-0.3V to Min (VCC + 0.3V, 6V) REFIN/OUT, REFCOMP .....-0.3V to Min (VCC + 0.3V, 6V) PORSEL, CA0, CA1, CA2 ..-0.3V to Min (VCC + 0.3V, 6V)
Operating Temperature Range LTC2655C ................................................ 0C to 70C LTC2655I .............................................-40C to 85C Maximum Junction Temperature .......................... 150C Storage Temperature Range ......................-65 to 150C Lead Temperature, GN Only (Soldering, 10 sec).... 300C
PIN CONFIGURATION
TOP VIEW REFLO GND DNC DNC 15 DNC 14 VOUTD 21 GND 13 VOUTC 12 PORSEL 11 CA0 6 CA2 7 SCL 8 DNC 9 10 SDA CA1 TOP VIEW REFLO VOUTA REFCOMP VOUTB REFIN/OUT LDAC CA2 SCL 1 2 3 4 5 6 7 8 16 GND 15 VCC 14 VOUTD 13 VOUTC 12 PORSEL 11 CA0 10 CA1 9 SDA VOUTA 1 REFCOMP 2 VOUTB 3 REFIN/OUT 4 LDAC 5 VCC
20 19 18 17 16
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150C, JA = 110C/W
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 150C, JA = 37C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
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LTC2655 ORDER INFORMATION
LTC2655 B C UF -L 16 #TR PBF
LEAD FREE DESIGNATOR
TAPE AND REEL TR = Tape and Reel RESOLUTION 16 = 16-Bit 12 = 12-Bit FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UF = 20-Lead (4mm x 4mm) Plastic QFN GN = 16-Lead Narrow SSOP TEMPERATURE GRADE C = Commercial Temperature Range (0C to 70C) I = Industrial Temperature Range (-40C to 85C) ELECTRICAL GRADE (OPTIONAL) B = 4LSB Maximum INL (16-Bit) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2655 PRODUCT SELECTION GUIDE
LEAD FREE FINISH LTC2655BCGN-L16#PBF LTC2655BIGN-L16#PBF LTC2655BCUF-L16#PBF LTC2655BIUF-L16#PBF LTC2655BCGN-H16#PBF LTC2655BIGN-H16#PBF LTC2655BCUF-H16#PBF LTC2655BIUF-H16#PBF LTC2655CGN-L12#PBF LTC2655IGN-L12#PBF LTC2655CUF-L12#PBF LTC2655IUF-L12#PBF LTC2655CGN-H12#PBF LTC2655IGN-H12#PBF LTC2655CUF-H12#PBF LTC2655IUF-H12#PBF TAPE AND REEL LTC2655BCGN-L16#TRPBF LTC2655BIGN-L16#TRPBF LTC2655BCUF-L16#TRPBF LTC2655BIUF-L16#TRPBF LTC2655BIGN-H16#TRPBF LTC2655BCUF-H16#TRPBF LTC2655BIUF-H16#TRPBF LTC2655CGN-L12#TRPBF LTC2655IGN-L12#TRPBF LTC2655CUF-L12#TRPBF LTC2655IUF-L12#TRPBF LTC2655CGN-H12#TRPBF LTC2655IGN-H12#TRPBF LTC2655CUF-H12#TRPBF LTC2655IUF-H12#TRPBF PART MARKING* PACKAGE DESCRIPTION 655L16 655L16 55L16 55L16 655H16 55H16 55H16 655L12 655L12 55L12 55L12 655H12 655H12 55H12 55H12 16-Lead Narrow SSOP 16-Lead Narrow SSOP 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN 16-Lead Narrow SSOP 16-Lead Narrow SSOP 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN 16-Lead Narrow SSOP 16-Lead Narrow SSOP 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN 16-Lead Narrow SSOP 16-Lead Narrow SSOP 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C MAXIMUM INL 4 4 4 4 4 4 4 4 1 1 1 1 1 1 1 1
LTC2655BCGN-H16#TRPBF 655H16
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2655 ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655-12 SYMBOL PARAMETER Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity (Note 3) Load Regulation (Note 3) (Note 3) VCC = 5.5V, VREF = 2.5V VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VCC = 3V 10%, Internal Reference, Mid-Scale, -7.5mA IOUT 5mA ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient
l
LTC2655B-L16/ LTC2655-L12 (Internal Reference=1.25V)
LTC2655B-16 MAX MIN 16 16 0.1 0.5 0.04 0.06 1 1 5 0.02 1 0.1 0.5 1 0.125 0.25 3 2 0.3 2 0.6 1 1 1 5 0.02 1 0.1 1 4 2 4 3 2 TYP MAX UNITS Bits Bits LSB LSB LSB/mA LSB/mA mV mV V/C %FSR ppm/C CONDITIONS
l l l l l l l
MIN 12 12
TYP
DC Performance
VREF = 1.25V (Note 4)
l
SYMBOL VOUT PSR ROUT
PARAMETER DAC Output Span Power Supply Rejection DC Output Impedance
CONDITIONS Internal Reference External Reference = VEXTREF VCC 10% VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VCC = 3V 10%, Internal Reference, Mid-Scale, -7.5mA IOUT 7.5mA Due to Full-Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V VEXTREF = 2.8V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND VCC = 2.7V VEXTREF = 1.4V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND
l l l l l l
MIN
TYP 0 to 2.5 0 to 2*VEXTREF -80 0.04 0.04 1.5 2 1
MAX
UNITS V V dB
0.15 0.15
V V/mA V
DC Crosstalk (Note 5)
ISC
Short-Circuit Output Current (Note 6)
20 20 10 10
65 65 45 45
mA mA mA mA
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LTC2655 ELECTRICAL CHARACTERISTICS
SYMBOL Reference Reference Output Voltage Reference Temperature Coefficient Reference Line Regulation Reference Short-Circuit Current REFCOMP Pin Short-Circuit Current Reference Load Regulation Reference Output Voltage Noise Density Reference Input Range Reference Input Current Reference Input Capacitance Power Supply VCC ICC Positive Supply Voltage Supply Current (Note 8) For Specified Performance VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off VCC = 3V, Internal Reference On VCC = 3V, Internal Reference Off
l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
PARAMETER CONDITIONS MIN 1.248 (Note 7) VCC 10% VCC = 5.5V, Forcing REFIN/OUT to GND VCC = 5.5V, Forcing REFCOMP to GND VCC = 3V10% or 5V10%, IOUT = 100A Sourcing , CREFCOMP = CREFIN/OUT = 0.1F at f = 1kHz External Reference Mode (Note 14) (Note 9) 2.7 1.7 1.3 1.6 1.2
l l l l
LTC2655B-L16/LTC2655-L12 (Internal Reference = 1.25V)
TYP 1.25 2 -80 3 65 40 30 0.5 0.001 20 5.5 2.5 2 2.2 1.7 3 0.3VCC 0.7VCC 0.8 0.6 2.4 2 0.15VCC 0.85VCC 10 10 2 0 20+0.1CB
l
MAX 1.252 10 5 200
UNITS V ppm/C dB mA A mV/mA nV/Hz
VCC /2 1
V A pF V mA mA mA mA A V V V V V V V V k k M
ISD Digital I/O VIL VIH VIL(LDAC) VIH(LDAC) VIL(CA) VIH(CA) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAn
Supply Current in Shutdown Mode (Note 8) VCC = 5V Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage (LDAC) High Level Input Voltage (LDAC) Low Level Input Voltage (CA0 to CA2) High Level Input Voltage (CA0 to CA2) Resistance from CAn (n = 0,1,2) to VCC to Set CAn = VCC Resistance from CAn (n = 0,1,2) to GND to Set CAn = GND Resistance from CAn (n = 0,1,2) to VCC or GND to Set Can = FLOAT Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitance Load for Each Bus Line External Capacitive Load on Address Pins CA0, CA1 and CA2 0.1VCC VIN 0.9VCC (Note 9) VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current =3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 13)
l l l l l l l l l l
0.4 250 50 1 10 400 10
V ns ns A pF pF pF
0
l l l l
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LTC2655 ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2655-12 SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity (Note 3) Load Regulation ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient
l l
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
LTC2655B-16 MAX MIN 16 16 0.1 0.5 0.04 1 1 5 0.02 1 0.1 0.5 1 0.125 3 2 0.3 2 0.6 1 1 5 0.02 1 0.1 1 4 2 3 2 TYP MAX UNITS Bits Bits LSB LSB LSB/mA mV mV V/C %FSR ppm/C CONDITIONS MIN 12 12 TYP
(Note 3) (Note 3) VCC = 5.5V, VREF = 2.5V VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA VREF = 2.048V (Note 4)
l l l l l l
SYMBOL VOUT PSR ROUT
PARAMETER DAC Output Span Power Supply Rejection DC Output Impedance DC Crosstalk
CONDITIONS Internal Reference External Reference = VEXTREF VCC 10% VCC = 5V 10%, Internal Reference, Mid-Scale, -15mA IOUT 15mA Due to Full Scale Output Change Due to Load Current Change Due to Powering Down (per Channel) VCC = 5.5V VEXTREF = 2.8V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND
l l l
MIN
TYP 0 to 4.096 0 to 2*VEXTREF -80 0.04 1.5 2 1
MAX
UNITS V V dB
0.15
V V/mA V
ISC
Short-Circuit Output Current (Note 4)
20 20
65 65
mA mA
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LTC2655 ELECTRICAL CHARACTERISTICS
SYMBOL Reference Reference Output Voltage Reference Temperature Coefficient Reference Line Regulation Reference Short-Circuit Current REFCOMP Pin Short-Circuit Current Reference Load Regulation Reference Output Voltage Noise Density Reference Input Range Reference Input Current Reference Input Capacitance Power Supply VCC ICC ISD Digital I/O VIL VIH VIL(LDAC) VIH(LDAC) VIL(CA) VIH(CA) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAn Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage (LDAC) High Level Input Voltage (LDAC) Low Level Input Voltage (CA0 to CA2) High Level Input Voltage (CA0 to CA2) Resistance from CAn (n = 0,1,2) to VCC to Set CAn = VCC Resistance from CAn (n = 0,1,2) to GND to Set CAn = GND Resistance from CAn (n = 0,1,2) to VCC or GND to Set CAn = FLOAT Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitance Load for Each Bus Line External Capacitive Load on Address Pins CA0, CA1 and CA2 0.1VCC VIN 0.9VCC (Note 9) VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 13)
l l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
PARAMETER CONDITIONS MIN 2.044 (Note 7) VCC 10% VCC = 5.5V, Forcing REFIN/OUT to GND VCC = 5.5V, Forcing REFCOMP to GND VCC = 5V10%, IOUT = 100A Sourcing , CREFCOMP = CREFIN/OUT = 0.1F at f = 1kHz External Reference Mode (Note 14) (Note 9) For Specified Performance VCC = 5V, Internal Reference On VCC = 5V, Internal Reference Off VCC = 5V
l l l l l l l l l
LTC2655B-H16/LTC2655-H12 (Internal Reference = 2.048V)
TYP 2.048 2 -80 3 65 40 35 0.5 0.001 20 4.5 1.9 1.5 5.5 2.5 2 3 0.3VCC 0.7VCC 0.8 2.4 0.15VCC 0.85VCC 10 10 2 0 20+0.1CB 0 0.4 250 50 1 10 400 10 VCC /2 1 5 200 MAX 2.052 10 UNITS V ppm/C dB mA A mV/mA nV/Hz V A pF V mA mA A V V V V V V k k M V ns ns A pF pF pF
Positive Supply Voltage Supply Current (Note 8) Supply Current in Shutdown Mode (Note 8)
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LTC2655 ELECTRICAL CHARACTERISTICS
SYMBOL ts PARAMETER Settling Time ( Note 10) Settling Time for 1LSB Step Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse (Note 11) DAC to DAC Crosstalk (Note 12) Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise At f = 1kHz At f = 10kHz 0.1Hz to 10Hz, Internal Reference (-L Options) 0.1Hz to 10Hz, Internal Reference (-H Options) 0.1Hz to 200KHz, Internal Reference (-L Options) 0.1Hz to 200KHz, Internal Reference (-H Options) At Mid-Scale Transition, -L Option At Mid-Scale Transition, -H Option CREFCOMP = CREFIN/OUT = 0.22F
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V (LTC2655B-H16, LTC2655-H12), VOUT unloaded unless otherwise specified. LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12
CONDITIONS 0.024%(1LSB at 12 Bits) 0.0015%(1LSB at 16 Bits) 0.024%(1LSB at 12 Bits) 0.0015%(1LSB at 16 Bits) MIN TYP 3.9 9.1 2.4 4.5 1.8 1000 4 7 0.5 150 85 80 8 12 400 450 MAX UNITS s s s s V/s pF nV*s nV*s nV*s kHz nV/Hz nV/Hz VP-P VP-P VP-P VP-P AC Performance
TIMING CHARACTERISTICS
SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF t1 t2 PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Clock Pin High Period of the SCL Clock Pin
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V (LTC2655B-H16, LTC2655-H12), VOUT unloaded unless otherwise specified.
CONDITIONS
l l l l l l l l l l l l l
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12 (see Figure 1)
MIN 0 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6 1.3 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns ns ns s s ns ns
Set-Up Time for a Repeated Start Program Data Hold Time Data Set-Up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Stop and Start Condition Falling edge of the 9th Clock of the 3rd Input Byte to LDAC High or Low Transition LDAC Low Pulse Width (Note 13) (Note 13)
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LTC2655 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: Linearity and monotonicity are defined from code kL to code 2N-1, where N is the resolution and kL is the lower end code for which no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is defined from code 128 to code 65535. For VREF = 2.5V and N = 12, kL =8 and linearity is defined from code 8 to code 4095. Note 4: Inferred from measurement at code 128 (LTC2655-16), or code 8 (LTC2655-12). Note 5: DC Crosstalk is measured with VCC = 5V and using internal reference, with the measured DAC at mid-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Maximum temperature coefficient is guaranteed for C-grade only. Note 8: Digital inputs at 0V or VCC. Note 9: Guaranteed by design and not production tested. Note 10: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 11: VCC = 5V (-H Options) or VCC = 3V (-L Options), internal reference mode. DAC is stepped 1 LSB between half-scale and half-scale - 1. Load is 2k n parallel with 200pF to GND. Note 12: DAC to DAC Crosstalk is the glitch that appears at the output of one DAC due to a full scale change at the output of another DAC. It is measured with VCC = 5V and using internal reference, with the measured DAC at mid-scale. Note 13: CB = Capacitance of one bus line in pF . Note 14: Gain error specification may be degraded for reference input voltages less than 1V. See Gain Error vs Reference Input Curve in the Typical Performance Characteristics section.
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LTC2655 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2655-L16
Integral Nonlinearity (INL)
4 3 2 DNL (LSB) INL (LSB) 1 0 -1 -2 -3 -4 128 16384 32768 CODE 49152 65535
2655 G01
TA = 25C unless otherwise noted.
Differential Nonlinearity (DNL)
1.0 VCC = 3V
VCC = 3V
0.5
0
-0.5
-1.0 128
16384
32768 CODE
49152
65535
2655 G02
INL vs Temperature
4 3 2 INL (LSB) 1 0 -1 -2 -3 -4 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G03
DNL vs Temperature
1.0 VCC = 3V 1.253 1.252
REFIN/OUT Output Voltage vs Temperature
VCC = 3V
VCC = 3V
INL(POS) DNL (LSB)
0.5 1.251 VREF (V)
2655 G04
DNL(POS) 0 DNL(NEG)
1.250 1.249
INL(NEG)
-0.5 1.248 -1.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C) 1.247 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G05
Settling to 1LSB Rising
SCL 3V/DIV 9TH CLOCK OF 3RD DATA BYTE VOUT 200V/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.50V VOUT 250V/DIV 7.8s SCL 3V/DIV
Settling to 1LSB Falling
7.3s 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.50V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 9TH CLOCK OF 3RD DATA BYTE
2655 G06
2655 G07
2s/DIV
2s/DIV
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LTC2655 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2655-H16
Integral Nonlinearity (INL)
4 3 2 DNL (LSB) INL (LSB) 1 0 -1 -2 -3 -4 128 16384 32768 CODE 49152 65535
2655 G08
TA = 25C unless otherwise noted.
Differential Nonlinearity (DNL)
1.0 VCC = 5V
VCC = 5V
0.5
0
-0.5
-1.0 128
16384
32768 CODE
49152
65535
2655 G09
INL vs Temperature
4 3 2 INL (LSB) 1 0 -1 -2 -3 -4 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G10
DNL vs Temperature
1.0 VCC = 3V 2.054 2.052
Reference Output Voltage vs Temperature
VCC = 5V
VCC = 3V INL(POS) DNL (LSB)
0.5 2.050 0 DNL(NEG) VREF (V)
2655 G11
DNL(POS)
2.048 2.046
INL(NEG)
-0.5 2.044 -1.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C) 2.042 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G12
Settling to 1LSB Rising
SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF VOUT 250V/DIV 7.9s SCL 5V/DIV VOUT 250V/DIV
Settling to 1LSB Falling
5.5s 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.096V RL = 2k, CL = 200pF 9TH CLOCK OF 3RD DATA BYTE
2655 G13
2655 G14
2s/DIV
2s/DIV
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LTC2655 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2655-12
Integral Nonlinearity (INL)
1.0 VCC = 5V VREF = 2.048V 1.0
TA = 25C unless otherwise noted.
Differential Nonlinearity (INL)
VCC = 3V VREF = 1.25V SCL 3V/DIV
Settling to 1LSB Falling
0.5 DNL (LSB) INL (LSB)
0.5 4.0s 0 VOUT 1mV/DIV 3/4 TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 8 1024 2048 CODE 3072 4095
2655 G16 2655 G17
0
-0.5
-0.5
-1.0
-1.0 8 1024 2048 CODE 3072 4095
2655 G15
2s/DIV
LTC2655
Load Regulation
10 INTERNAL REF 8 CODE = MID-SCALE 6 4 VOUT (mV) VOUT (V) 2 0 -2 -4 -6 VCC = 5V (LTC2655-H) -8 VCC = 3V (LTC2655-L) -10 -50 -40 -30 -20 -10 0 10 20 30 40 50 IOUT (mA)
2655 G18
Current Limiting
0.20 INTERNAL REF 0.15 CODE = MID-SCALE 0.10 VOUT (V) 0.05 0 -0.05 -0.10 -0.15 VCC = 5V (LTC2655-H) VCC = 3V (LTC2655-L) -0.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 IOUT (mA)
2655 G19
Headroom at Rails vs Output Current
5.0 4.5 5V (LTC2655-H) SOURCING 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5V (LTC2655-H) SINKING 3V (LTC2655-L) SOURCING
0.5 3V (LTC2655-L) SINKING 0 0 1 2 3 456 IOUT (mA) 7 8 9 10
2655 G20
Offset Error vs Temperature
3 2 ZERO-SCALE ERROR (mV) OFFSET ERROR (mV) 1 0 -1 -2 -3 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G21
Zero-Scale Error vs Temperature
3.0 2.5 2.0 1.5 1.0 0.5 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G22
Gain Error vs Temperature
64 48 32 GAIN ERROR (LSB) 16 0 -16 -32 -48 -64 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G23
LTC2655-16
2655f
13
LTC2655 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2655
Offset Error vs Reference Input
2.0 64 VCC = 5V 1.5 OFFSET ERROR OF 4 CHANNELS OFFSET ERROR (mV) GAIN ERROR (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2 0.5 1 1.5 2 REFERENCE VOLTAGE (V) 2.5
2655 G24
TA = 25C unless otherwise noted.
Gain Error vs Reference Input
LTC2655-16 48 VCC = 5.5V GAIN ERROR OF 4 CHANNELS 32 16 ICC (nA) 0 -16 -32 -48 -64 0.5 1 1.5 2 REFERENCE VOLTAGE (V) 2.5
2655 G25
ICC Shutdown vs VCC
450 400 350 300 250 200 150 100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
2655 G26
Supply Current vs Logic Voltage
2.6 SWEEP SCL AND SDA BETWEEN 2.4 0V AND VCC SUPPLY CURRENT (mA) 2.2 ICC (mA) VCC = 5V (LTC2655-H) 2.0 1.8 1.6 1.4 3.0
Supply Current vs Temperature
5
ICC Shutdown vs Temperature
4 ICC SHUTDOWN (A) 2.5 LTC2655-H VCC = 5V
2.0
LTC2655-H VCC = 5V, CODE = MS INTERNAL REFERENCE LTC2655-L VCC = 3V, CODE = MS INTERNAL REFERENCE
3
2
VCC = 3V (LTC2655-L)
1.5
1 LTC2655-L VCC = 3V 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G29
0
1
2 3 LOGIC VOLTAGE (V)
4
5
2655 G27
1.0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
2655 G28
Multiplying Bandwidth
8 6 4 AMPLITUDE (dB) 2 0 -2 -4 -6 -8 -10 -12 1k VS = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE 10k 100k FREQUENCY (Hz) 1M
2655 G30
Large-Signal Response
VCC = 5V, VREF = 2.048V ZERO-SCALE TO FULL-SCALE SCL 5V/DIV
Mid-Scale Glitch Impulse
9TH CLOCK OF 3RD DATA BYTE
VOUT 1V/DIV
VOUT 5mV/DIV
LTC2655-H16, VCC = 5V 7nV-s TYP
LTC2655-L16, VCC = 3V 4nV-s TYP
2655 G31
2655 G32
2s/DIV
2s/DIV
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14
LTC2655 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2655
DAC to DAC Crosstalk (Dynamic)
ONE DAC SWITCH 0-FS 1V/DIV
TA = 25C unless otherwise noted.
Power-On Reset Glitch
VCC 2V/DIV
VOUT 0.5mV/DIV LTC2655-L16, VCC = 5V, 0.4nV*s TYP CREFCOMP = CREFOUT = 0.22F
2655 G33
VOUT 10mV/DIV
ZERO-SCALE
2655 G34
2s/DIV
200s/DIV
Power-On Reset to Mid-Scale
LTC2655-L 400
Noise Voltage vs Frequency
VCC = 5V CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1F
NOISE VOLTAGE (nV/Hz)
VCC 2V/DIV
300
200 LTC2655-H 100 LTC2655-L
VOUT 1V/DIV
2655 G35
0
1ms/DIV
10
100
1k 10k FREQUENCY (Hz)
100k
1M
2655 G36
DAC Output 0.1Hz to 10Hz Voltage Noise
VCC = 5V, LTC2655-H CODE = MID-SCALE INTERNAL REF CREFCOMP = CREFOUT = 0.1F
Reference 0.1Hz to 10Hz Voltage Noise
VREFOUT = 2.048V CREFCOMP = CREFOUT = 0.1F
5V/DIV
2V/DIV
2655 G37
2655 G38
1s/DIV
1s/DIV
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15
LTC2655 PIN FUNCTIONS
(GN/UF)
REFLO (Pin 1/Pin 20): Reference Low. The voltage at this pin sets the zero-scale voltage of all DACs. This pin should be tied to GND. VOUTA to VOUTD (Pins 2,4,13,14/Pins 1, 3, 13, 14): DAC Analog Voltage Outputs. The output range is 0V to 2 times the voltage at the REFIN/OUT pin. REFCOMP (Pin 3/Pin 2): Internal Reference Compensation. For low noise and reference stability, tie 0.1F capacitor to GND. Connect to GND to use an external reference at start-up. Command 0111b must still be issued to turn off internal reference. REFIN/OUT (Pin 5/Pin 4): This pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. When acting as an output the nominal voltage at this pin is 1.25V for -L options and 2.048V for -H options. For low noise and reference stability tie a capacitor from this pin to GND. Capacitor value must be CREFCOMP. In external reference mode, the allowable reference input voltage range is 0.5V to VCC /2. LDAC (Pin 6/Pin 5): Asynchronous DAC Update. A falling edge on this input after four bytes have been written into the part, immediately updates the DAC register with the contents of the input register. A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. Software power-down is disabled when LDAC is low. CA2 (Pin 7/Pin 6): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2).
SCL (Pin 8/Pin 7): Serial Clock Input. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 9/Pin 9): Serial Data Bidirectional. Data is shifted into the SDA pin and acknowledged by the SDA pin. This is a high impedance pin while data is shifted in. It is an opendrain N-channel output during acknowledgement. This pin requires a pull-up resistor or current source to VCC. CA1 (Pin 10/Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). CA0 (Pin 11/Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 2). PORSEL (Pin 12/Pin 12): Power-On-Reset Select. If tied to GND, the part resets to zero-scale at power-up, if tied to VCC, the part resets to mid-scale. VCC (Pin 15/Pin 18): Supply Voltage Input. For -L options, 2.7V VCC 5.5V, and for -H options, 4.5V VCC 5.5V. Bypass to ground with a 0.1F capacitor placed as close to pin as possible. GND (Pin 16/Pin 19, Exposed Pad Pin 21): Ground. Must be soldered to PCB Ground. DNC (NA/Pins 8, 15, 16, 17): Do not connect these pins.
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16
LTC2655 BLOCK DIAGRAM
REFCOMP GND REFLO REGISTER REGISTER REGISTER REGISTER VOUTA DAC A DAC D VOUTD INTERNAL REFERENCE REFIN/OUT
VCC
REGISTER
REGISTER
REGISTER
VOUTB CA0 CA1
REGISTER
DAC B
DAC C
VOUTC
32-BIT SHIFT REGISTER CA2 SCL LDAC 2-WIRE INTERFACE
POWER-ON RESET
PORSEL
SDA
2655 BD
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17
LTC2655 TEST CIRCUITS
Test Circuit 1
100 CAn VIH(CAn)/VIL(CAn)
2655 TC01
Test Circuit 2
VDD
RINH/RINL/RINF
2655 TC02
GND
TIMING DIAGRAM
SDA tf SCL tHD(STA) tSU(STA) tSU(STO) tLOW tr tSU(DAT) tf tHD(STA) tSP tr tBUF
S
tHD(DAT)
tHIGH
S
P
S
2655 F01
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
9TH CLOCK OF 3RD DATA BYTE SCL t1 LDAC
Figure 1
2655f
18
LTC2655 OPERATION
The LTC2655 is a family of quad voltage output DACs in 20-lead 4mm x 4mm QFN and in 16-lead narrow SSOP packages. Each DAC can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. Four combinations of accuracy (16-bit and 12-bit), and full-scale voltage (2.5V or 4.096V) are available. The LTC2655 is controlled using a 2-wire I2C compatible interface. Power-On Reset The LTC2655-L/LTC2655-H clear the output to zero-scale if PORSEL pin is tied to GND, when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2655 contains circuitry to reduce the power-on glitch. The analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Alternatively, if PORSEL pin is tied to VCC, The LTC2655-L/ LTC2655-H set the output to mid-scale when power is first applied. Power Supply Sequencing and Start-Up For the LTC2655 family of parts, the internal reference is powered up at start-up by default. If an external reference is to be used, REFCOMP (Pin 3/Pin 2, GN/UF) must be hardwired to GND. This configuration allows the use of an external reference at start-up and converts the REFIN/OUT pin to an input. However, the internal reference will still be ON and draw supply current. In order to use an external reference, command 0111b should be used to turn the internal reference off (see Table 1). The voltage at REFIN/OUT (Pin 5/Pin 4, GN/UF) should be kept within the range - 0.3V REFIN/OUT VCC + 0.3V (see the Absolute Maximum Ratings section). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 15/Pin 18, GN/UF) is in transition. Transfer Function The digital-to-analog transfer function is VOUT(IDEAL) = 2 * k/2N [VREF - REFLO] + REFLO where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is the voltage at the REFIN/OUT Pin. The resulting DAC output span is 0V to 2*VREF, as it is necessary to tie REFLO to GND. VREF is nominally 1.25V for LTC2655-L and 2.048V for LTC2655-H, in internal reference mode.
Table 1
COMMAND* C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 Write to Input Register n 1 Update (Power-Up) DAC Register n 0 Write to Input Register n, Update (Power-Up) All 1 Write to and Update (Power-Up) n 0 Power-Down n 1 Power-Down Chip (All DAC's and Reference) 0 Select Internal Reference (Power-Up Reference) 1 Select External Reference (Power-Down Reference) 1 No Operation
ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 DAC A 1 DAC B 0 DAC C 1 DAC D 1 All DACs
* Command and address codes not shown are reserved and should not be used.
Serial Interface The LTC2655 communicates with a host using the standard 2-wire I2C interface. The Timing Diagram (Figure 1) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be
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19
LTC2655 OPERATION
necessary if the bus capacitance is greater than 200pF . The LTC2655 is a receive-only (slave) device. The master can write to the LTC2655. The LTC2655 does not respond to a read command from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition (see Figure 1). A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2655 responds to a write by a master in this manner. The LTC2655 does not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC , GND or float. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 2. In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2655 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit on-chip hardwired address and is not selectable by CA0, CA1 and CA2. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 2. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF as these pins are driven during address , detection to determine if they are floating.
Table 2. Slave Address Map
CA2 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VCC VCC VCC VCC VCC VCC VCC VCC VCC CA1 GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC CA0 GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC A6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
GLOBAL ADDRESS
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20
LTC2655 OPERATION
Write Word Protocol The master initiates communication with the LTC2655 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2655 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of write data. The LTC2655 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2655 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2655 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The first byte of the input word consists of the 4-bit command followed by the 4-bit address. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-bit, or 12-bit input code, MSB to LSB, followed by 0 or 4 don't care bits (LTC2655-16 and LTC2655-12 respectively). A typical LTC2655 write transaction is shown in Figure 2. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four outputs are needed. When in power-down, the buffer amplifiers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The integrated reference is automatically powered down when external reference mode is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using the Power-Down Chip command 0101b. For all power-down commands the 16-bit data word is ignored, but still required in order to complete a full communication cycle. Normal operation resumes by executing any command which includes a DAC update, in software as shown in Table 1 or using the asynchronous LDAC pin. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is approximately 12s. If on the other hand, all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and the integrated reference.
2655f
21
LTC2655 OPERATION
In this case, the power-up delay time is approximately 14s. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference command (0111b), then it can only be powered back up by sending the Select Internal Reference command (0110b). However if the reference was powered down by sending the Power-Down Chip command (0101b), then in addition to the Select Internal Reference command (0110b), any command that powers up the DACs will also power-up the integrated reference. Reference Modes For applications where an accurate external reference is not available, the LTC2655 has a user-selectable, integrated reference. The LTC2655-L has a 1.25V reference that provides a full-scale output of 2.5V. The LTC2655-H has a 2.048V reference that provides a full-scale output of 4.096V. Both references exhibit a typical temperature drift of 2ppm/C. Internal reference mode can be selected by using command 0110b, and is the power-on default. A buffer is needed if the internal reference is required to drive external circuitry. For reference stability and low noise, it is recommended that a 0.1F capacitor be tied between REFCOMP and GND. In this configuration, the internal reference can drive up to 0.1F capacitive load without any stability problems. In order to ensure stable operation, the capacitive load on the REFIN/OUT pin should not exceed the capacitive load on the REFCOMP pin. The DAC can also operate in external reference mode using command 0111b. In this mode, the REFIN/OUT pin acts as an input that sets the DAC's reference voltage. This input is high impedance and does not load the external reference source. The acceptable voltage range at this pin is 0.5V REFIN/OUT VCC /2. The resulting full-scale output voltage is 2*VREFIN/OUT. For using external reference at start-up, see the Power Supply Sequencing and Start-Up Sections. Integrated Reference Buffers Each of the four DACs in LTC2655 has its own integrated high performance reference buffer. The buffers have very high input impedance and do not load the reference voltage source. These buffers shield the reference voltage from glitches caused by DAC switching and thus minimize DAC-to-DAC dynamic crosstalk. By tying 0.22F capacitors between REFCOMP and GND, and also between REFIN/OUT and GND, the crosstalk can be reduced to less than 1nV*s. See the curve DAC-to-DAC Crosstalk (Dynamic) in the Typical Performance Characteristics section. Voltage Outputs Each of the four rail-to-rail amplifiers contained in LTC2655 has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifiers' DC output impedance is 0.040 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30 * 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF .
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22
LTC2655 OPERATION
Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be connected to analog ground. The REFLO pin should be connected to system star ground. Resistance from the REFLO pin to system star ground should be as low as possible. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur in external reference mode near full scale when the REFIN/OUT pin is at VCC/2. If VREFIN/OUT = VCC /2 and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREFIN/OUT (VCC - FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
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23
LTC2655
OPERATION
24
COMMAND SA0 C3 C3 ACK ACK C2 C1 C0 A3 A2 A1 A0 C2 C1 C0 A3 A2 A1 A0 WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 MS DATA LS DATA D4 D3 D2 D1 D0 STOP SA0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 ACK ACK 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE
2655 F02
SLAVE ADDRESS
SA6
SA5
SA4
SA3
SA2
SA1
START
SDA
SA6
SA5
SA4
SA3
SA2
SA1
SCL
1
2
3
4
5
6
VOUT
ZERO-SCALE VOLTAGE
Figure 2. Typical LTC2655 Input Waveform--Programming DAC Output for Full-Scale
2655f
LTC2655 OPERATION
POSITIVE FSE
VREF = VCC
VREF = VCC
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) INPUT CODE (b)
2655 F03
65, 535
0V NEGATIVE OFFSET
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero-Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
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25
LTC2655 PACKAGE DESCRIPTION
GN Package 16-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 BSC 1 .015 .004 x 45 (0.38 0.10) .0532 - .0688 (1.35 - 1.75) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249)
0 - 8 TYP
.016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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26
LTC2655 PACKAGE DESCRIPTION
UF Package 20-Lead (4mm x 4mm) Plastic QFN
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 0.05 4.50 0.05 3.10 0.05 2.00 REF 2.45 0.05 2.45 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 PIN 1 TOP MARK (NOTE 6) 2.00 REF 2.45 0.10 0.75 0.05 R = 0.05 TYP BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
19 20 0.40 0.10 1 2
4.00 0.10
2.45 0.10
(UF20) QFN 01-07 REV A
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
2655f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2655 TYPICAL APPLICATION
5V Bipolar Output DAC
+5V C2 0.1F C1 +5V 0.1F C3 0.1F 3
+ -
5 1 +12V 7 LT1991 8 50k M9 150k M3 M1 450k P1 150k P3 50k P9
2655 TA02
LTC6240IS5 4 2
VCC 450k 4pF
5 7 9 11 10 6
18
2
4
17
16 9 1 3 13 14 1 2 3 10 VOUTA VOUTB VOUTC VOUTD
TO MICROCONTROLLER
DNC DNC 8 15
19
21
20
12 5V
*PIN NUMBERS SHOWN ARE FOR THE QFN PACKAGE.
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC, SSOP-16 Package 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, SSOP-16 Package 260A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 3mm x 4mm DFN-12 Package 270A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 3mm x 3mm DFN-10 Package 4LSB INL, 1LSB DNL, 4mm x 4mm QFN-20, Narrow SSOP-16 Packages 4LSB INL, 1LSB DNL, 4mm x 5mm QFN-20, TSSOP-20 Packages 125A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 3mm x 3mm QFN-16 and MSOP-10 Packages 125A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 4mm x 3mm DFN-14 and MSOP-16 Packages 180A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 6-Lead SC70 Package (LTC2630), 8-Lead TSOT-23 (LTC2631) 60A, 0.75 LSB DNL, Rail-to-Rail, 5-Lead SOT-23 and MSOP-8 Packages Low Noise, Rail-to-Rail 100A Micropower, Pin Selectable Gain = -13 to 14 LTC2609/LTC2619/ Quad 16-/14-/12-Bit I2C VOUT DACs LTC2629 LTC2605/LTC2615/ Octal 16-/14-/12-Bit I2C VOUT DACs LTC2625 LTC2607/LTC2617/ Dual 16-/14-/12-Bit I2C VOUT DACs LTC2627 LTC2606/LTC2616/ Single 16-/14-/12-Bit I2C VOUT DACs LTC2626 LTC2654 LTC2656/LTC2657 LTC2634/LTC2635 LTC2636/LTC2637 LTC2630/LTC2631 LTC2641/LTC2642 LTC1669 LTC6240 LT1991 Quad 16-/12-Bit SPI VOUT DACs with 10ppm/C (Max) Reference Octal 16-/12-Bit SPI/I2C VOUT DACs with 10ppm/C (Max) Reference Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/C (Typ) Reference Octal 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/C (Typ) Reference Single 12-/10-/8-Bit SPI/I2C VOUT DACs with Bidirectional 10ppm/C (Typ) Reference 10-Bit I2C Interface VOUT Micropower DAC Single 18MHz, CMOS Op Amp Precision Gain Selectable Difference Amplifier
Single 16-/14-/12-Bit SPI VOUT DACs with 1LSB INL, DNL 1LSB (Max) INL, DNL, 120A, 3mm x 3mm DFN and MSOP Packages
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010
+ -
VEE 4 -12V
LDAC VCC REFCOMP REFIN/OUT SCL SDA CA0 LTC2655IUF-L16* CA1 CA2 GND GND REFLO PORSEL
DNC DNC
450k
450k 4pF REF 5
6 VOUT 5V
2655f LT 0710 * PRINTED IN USA

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